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1 ltc1433/ltc1434 450ma, low noise current mode step-down dc/dc converters n cellular telephones n portable instruments n wireless modems n rf communications n distributed power systems n scanners n battery-powered equipment descriptio n u n high efficiency: up to 93% n constant frequency adaptive power tm operation n input voltage range: 3v to 13.5v n internal 0.6 w power switch (v in = 10v) n low dropout operation: 100% duty cycle n low-battery detector n internal power-on reset timer n current mode operation for excellent line and load transient response n low quiescent current: 470 m a n shutdown mode draws only 15 m a supply current n 1% reference accuracy n available in 16- and 20-lead narrow ssop features the ltc ? 1433/ltc1434 are monolithic pulse width modu- lated step-down dc/dc converters. by utilizing current mode switching techniques, they provide excellent ac and dc load and line regulation. both devices operate at a fixed frequency with the ltc1434 phase-lockable to an external clock signal. both devices incorporate two internal p-channel power mosfets with a parallel combined resistance of 0.6 w (at a supply of 10v). the adaptive power output stage selec- tively drives one or both of the switches at frequencies up to 700khz to reduce switching losses and maintain high efficiencies at low output currents. the ltc1433/ltc1434 are capable of supplying up to 450ma of output current and boasts a 2.4% output voltage accuracy. an internal low-battery detector has the same level of accuracy as the output voltage. a power-on reset timer (por) is included which generates a signal delayed by 65536/f clk (300ms typ) after the output is within 5% of the regulated output voltage. ideal for current sensitive applications, the devices draw only 470 m a of quiescent current. in shutdown the devices draw a mere 15 m a. to further maximize the life of the battery source, the internal p-channel mosfet switch is turned on continuously in dropout. applicatio n s u , ltc and lt are registered trademarks of linear technology corporation. adaptive power is a trademark of linear technology corporation. typical applicatio n u 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssw nc bsw nc sgnd run/ss lbo lbi pwrv in sv in c osc por i th v osense v prog ltc1433 pgnd 68 m f** 20v 0.1 m f 0.1 m f 100 m f* 10v d1: motorola mbrs130lt3 l1: coilcraft d03316-104 v out 3.3v d1 l1 100 m h power-on reset v in 3.5v to 12v 680pf 5.1k 10k 6800pf 47pf 1433/34 f01 * avx tpsd107m010r0100 ** avx tpse686m020r0150 + + figure 1. high efficiency step-down converter load current (a) 0.001 60 efficiency (%) 70 80 0.01 0.1 1 1433/34 ta01 50 40 100 90 v in = 5v v in = 12v v in = 9v ltc1433 efficiency for v out = 3.3v
2 ltc1433/ltc1434 a u g w a w u w a r b s o lu t exi t i s (voltages referred to pgnd pin) input supply voltage (pwrv in , sv in ) ... 13.5v to C 0.3v dc small switch current (ssw) ......................... 100ma peak small switch current (ssw) ..................... 300ma small switch voltage (ssw) ................................ (v in + 0.3v) to (v in C 13.5v) dc large switch current (bsw) ....................... 600ma peak large switch current (bsw) .......................... 1.2a large switch voltage (bsw) ................................ (v in + 0.3v) to (v in C 13.5v) pllin, pll lpf, i th , c osc ........................ 2.7v to C 0.3v por, lbo .................................................. 12v to C 0.3v lbi, v osense .............................................. 10v to C 0.3v run/ss, v prog voltages v in 3 11.7v ...........................................12v to C 0.3v v in < 11.7v ............................... (v in + 0.3v) to C 0.3v commercial temperature range ltc1433c/ltc1434c .............................. 0 c to 70 c extended commercial operating temperature range (note 2) ....................................... C 40 c to 85 c industrial temperature range (note 3) ltc1433i/ltc1434i ........................... C 40 c to 85 c junction temperature (note 4)............................. 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c (note 1) wu u package / o rder i for atio order part number order part number ltc1433cgn ltc1433ign ltc1434cgn ltc1434ign t jmax = 125 c, q ja = 150 c/w t jmax = 125 c, q ja = 150 c/w 1 2 3 4 5 6 7 8 top view gn package 16-lead plastic ssop 16 15 14 13 12 11 10 9 ssw nc bsw nc sgnd run/ss lbo lbi pwrv in pgnd sv in c osc por i th v osense v prog consult factory for military grade parts. 1 2 3 4 5 6 7 8 9 10 top view gn package 20-lead plastic ssop 20 19 18 17 16 15 14 13 12 11 nc ssw nc bsw sgnd nc run/ss nc lbo lbi pwrv in pgnd sv in pllin pll lpf c osc por i th v osense v prog electrical characteristics t a = 25 c, v in = 10v, v run/ss = 5v, unless otherwise noted. (notes 2, 3) symbol parameter conditions min typ max units main control loop i in v osense feedback current v prog pin open (note 5) 10 50 na v osense regulated output voltage (note 5) 1.19v (adjustable) selected v prog pin open l 1.178 1.190 1.202 v 3.3v selected v prog = 0v l 3.220 3.300 3.380 v 5v selected v prog = v in l 4.880 5.000 5.120 v v ovl output overvoltage lockout v prog pin open 1.24 1.28 1.32 v d v osense reference voltage line regulation v in = 3.6v to 13v (note 5), v prog pin open 0.002 0.01 %/v v loadreg output voltage load regulation i th sinking 5 m a (note 5) l 0.5 0.8 % i th sourcing 5 m a (note 5) l C 0.5 C 0.8 %
3 ltc1433/ltc1434 electrical characteristics t a = 25 c, v in = 10v, v run/ss = 5v, unless otherwise noted. the l denotes specifications which apply over the specified temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: c-grade device specifications are guaranteed over the 0 c to 70 c temperature range. in addition, c-grade device specifications are assured over the C 40 c to 85 c temperature range by design or correlation, but are not production tested. note 3: i-grade device specifications are guaranteed over the C 40 c to 85 c temperature range by design, testing or correlation. note 4: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc1433/ltc1434: t j = t a + (p d )(150 c/w) note 5: the ltc1433/ltc1434 are tested in a feedback loop which servos v osense to the feedback point for the error amplifier (v ith = 1.19v). note 6: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. note 7: oscillator frequency is tested by measuring the c osc charge and discharge currents and applying the formula: f osc (khz) = + ? 8.4(10 8 ) c osc (pf) + 11 () 1 i chg () 1 i dis symbol parameter conditions min typ max units i prog v prog input current 0.5v > v prog C4 C10 m a v in C 0.5v < v prog < v in 4 10 m a main control loop i q input dc supply current (note 6) normal mode 3.6v < v in < 13v 470 m a shutdown, reference alive v run/ss = 0v, 3.6v < v in < 13v, lbi > 0.9v 35 70 m a complete shutdown v run/ss = 0v, 3.6v < v in < 13v, lbi 0.48v 15 30 m a v run/ss run/ss threshold l 0.8 1.3 2 v i run/ss soft start current source v run/ss = 0v 1.2 3 4.5 m a oscillator and phase-locked loop f osc oscillator frequency c osc = 100pf (note 7) 112 125 142 khz v co high v pll lpf = 2.4v 200 240 khz r pllin pll input resistance 50 k w i pll lpf phase detector output current sinking capability f pllin < f osc 10 15 20 m a sourcing capability f pllin > f osc 10 15 20 m a power-on reset v satpor por saturation voltage i por = 1.6ma, v osense = 1v, v prog open 0.6 1.0 v i lpor por leakage v por = 10v, v osense = 1.2v, v prog open 0.2 1.0 m a v trpor por trip voltage from regulated v prog pin open, v osense ramping negative C 11 C 7.5 C 4 % output t dpor por delay v prog pin open 65536 cycles low-battery comparator v satlbo lbo saturation voltage i lbo = 1.6ma, v lbi = 1.1v 0.6 1.0 v i llbo lbo leakage v lbo = 10v, v lbi = 1.4v 0.01 1.0 m a v trlbi lbi trip voltage high to low transition on lbo 1.16 1.19 1.22 v v hystlb low-battery comparator hysteresis 40 mv v sdlb low-battery shutdown trip point 0.74 v i inlbi lbi input current v lbi = 1.19v 1 50 na p-channel power fets characteristics r smfet r ds(on) of small fet i ssw = 15ma 3.3 4.1 w r bigfet r ds(on) of big fet i bsw = 150ma 0.8 1.2 w i lssw small fet leakage v run/ss = 0v l 7 1000 na i lbsw big fet leakage v run/ss = 0v l 5 1000 na
4 ltc1433/ltc1434 typical perfor m a n ce characteristics u w load current (a) 0.001 60 efficiency (%) 70 80 0.01 0.1 1 1433/34 g01 50 40 100 90 v in = 5v v in = 12v v in = 3.6v v out = 3.3v l = 22 m h c soc = 47pf efficiency of figure 1 for l = 22 m h supply voltage (v) 3.2 output voltage (v) 3.0 3.2 3.4 4.8 1433/34 g03 2.8 2.6 2.9 3.1 3.3 2.7 2.5 2.4 3.6 4.0 4.4 3.4 5.0 3.8 4.2 4.6 5.2 v prog = 0v l = 20 m h c osc = 50pf i out 300ma i out 400ma i out 500ma dropout characteristics at different load currents (v out = 3.3v) supply voltage (v) 3 360 supply current ( a) 380 400 420 440 57 9 11 1433/34 g02 460 480 46 8 10 supply current vs supply voltage dropout characteristics at different load currents (v out = 5v) maximum output current vs input supply supply voltage (v) 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 6.2 output voltage (v) 4.7 4.8 4.9 1433/34 g04 4.6 4.5 4.2 4.3 4.4 5.1 5.0 i out 200ma i out 400ma i out 300ma v prog = v in l = 20 m h c osc = 50pf supply voltage (v) 3 maximum output current (ma) 500 600 700 800 11 1433/34 g05 400 300 200 5 7 9 13 v out 3.3v v out 5v l = 22 m h c osc = 50pf reference voltage vs temperature temperature ( c) ?5 reference voltage (v) 1.186 1.194 115 1433/34 g06 1.178 1.170 ? 35 75 ?5 15 55 95 1.202 1.182 1.190 1.174 1.198 supply voltage (v) 3 r ds(on) of small fet ( w ) 6 8 11 1433/34 g07 4 2 5 7 3 1 0 5 7 9 412 6 8 10 13 t a = 25 c t a = 70 c t a = 0 c switch resistance of small fet switch leakage current vs temperature temperature ( c) 0 40 50 70 60 100 1433/34 g09 30 20 20 40 80 120 140 10 0 60 160 200 280 120 80 40 0 240 switch leakage at ssw pin (na) switch leakage at bsw pin (na) v in = 13.5v ssw pin bsw pin switch resistance of big fet supply voltage (v) 3 r ds(on) of big fet ( w ) 1.2 1.6 2.0 11 1433/34 g08 0.8 0.4 0 1.4 1.8 1.0 0.6 0.2 5 7 9 412 6 8 10 13 t a = 70 c t a = 0 c t a = 25 c
5 ltc1433/ltc1434 pi n fu n ctio n s uuu ssw (pin 1/pin 2): drain of the small p-channel mosfet switch. bsw (pin 3/pin 4): drain of the large p-channel mosfet switch. sgnd (pin 5): small-signal ground. must be routed separately from other grounds to the (C) terminal of c out . run/ss (pin 6/pin 7): combination of soft start and run control inputs. a capacitor to ground at this pin sets the ramp time to full current output. the time is approxi- mately 0.5s/ m f. forcing this pin below 1.3v causes all circuitry to be shut down except the low-battery com- parator. for input voltages above 6v this pin is clamped by a 6v zener (see functional diagram). applying voltages greater than 6v to this pin will cause additional current to flow into this pin. lbo (pin 7/pin 9): open-drain output of an n-channel pull-down. this pin will sink current when lbi goes below 1.19v. lbi (pin 8/pin 10): the (+) input of the low-battery voltage comparator. the (C) input is connected to the 1.19v reference. when lbi is grounded along with run/ ss, this comparator will shut down along with the rest of the control circuitry. lbo will go to high impedance. v prog (pin 9/pin 11): the voltage at this pin selects the output voltage. when v prog = 0v or v prog = v in , the output is set to 3.3v and 5v respectively, with v osense connected to the output. leaving v prog open (dc) allows the output voltage to be set by an external resistive divider. v osense is then connected to the common node of the resistive divider. v osense (pin 10/pin 12): this pin receives the feedback voltage either from the output or from an external resistive divider across the output. the v prog pin determines at which point v osense must be connected. v prog = 0v v out = 3.3v v prog = v in v out = 5v v prog = open (dc) v out = adjustable i th (pin 11/pin 13): error amplifier compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is 0v to 2.4v. por (pin 12/pin 14): open-drain output of an n-chan- nel pull-down. this pin sinks current when the output voltage is 7.5% out of regulation. when the output rises to C 5% of its regulated value, the pin goes into high impedance after 2 16 (65536) oscillator cycles. the por output is asserted when the device is in shutdown, independent of v out . c osc (pin 13/pin 15): external capacitor connects be- tween this pin and ground to set the operating frequency. pll lpf (pin 16 ltc1434): output of the phase detector and control input of the oscillator. normally a series rc lowpass network is connected from this pin to ground. tie this pin to sgnd in applications which do not use the phase-locked loop. can be driven by a 0v to 2.4v logic signal for a frequency shifting option. pllin (pin 17 ltc1434): external synchronizing input to the phase detector. this pin is internally terminated to sgnd with 50k w . tie this pin to sgnd in applications which do not use the phase-locked loop. sv in (pin 14/pin 18): main supply for all the control circuitry. pgnd (pin 15/pin 19): switch driver ground. connects to the (C) terminal of c in . anode of the schottky diode must be connected close to this pin. pwrv in (pin 16/pin 20): supply for the internal power mosfets and switch drivers. must decouple this pin properly to ground. nc (pins 2, 4,/pins 1, 3, 6, 8): no connection. (ltc1433/ltc1434)
6 ltc1433/ltc1434 fu n ctio n al diagra uu w operatio n u (refer to functional diagram) main control loop the ltc1433/ltc1434 is a constant frequency, pulse- width modulated current mode switching regulator. dur- ing normal operation, the internal p-channel power mosfet is turned on each cycle when the oscillator sets the rs latch ff3, and turned off when the main current compara- tor i comp resets the latch. the peak inductor current at which the i comp resets the rs latch is controlled by the voltage on the i th pin , which is the output of error amplifier gm. pins v prog and v osense , described in the pin func- tions section, allow gm to receive an output feedback voltage v fb from either the internal or external resistive dividers. when the load current increases, it causes a slight decrease in v fb relative to the 1.19v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. the main control loop is shut down by pulling the run/ss pin low. releasing run/ss allows an internal 3 m a current source to charge up the soft start capacitor c ss . when c ss reaches 1.3v, the main control loop is enabled with the i th voltage clamped at approximately 30% of its maximum value. as c ss continues to charge, i th is gradually re- leased allowing normal operation to resume. comparator ovdet guards against transient overshoots > 7.5% by turning off the p-channel power mosfets and keeping them off until the fault is removed. low current operation the ltc1433/ltc1434 have two internal p-channel mosfets sized for low and high load current conditions. at low load current, only the small mosfet will be turned on while at high load current both mosfets will be on. + + + + lobat + + + gm lidet ovdet por bsw pwrv in ssw i th lbi lbo v ref pll lpf pllin c osc 180k 0.6v sv in 30k 6v v ref + 89mv v set i peak det i comp 12mv run/ss 50k 120k ref and v cc shdn v ref (1.19v) v ref pgnd sgnd v cc sv in rb sb q q ff3 rb sb q q ff2 d ck q q ff1 por pll shdn shdn freq shift osc v co slope comp r sense 0.143 w voltage select 60k 240k 60k v prog v osense 1433/34 fd
7 ltc1433/ltc1434 operatio n u (refer to functional diagram) having only the small mosfet on with low load current reduces switching and gate charge losses, hence boosting efficiency. for the device to go into low current mode, two conditions must be satisfied: the peak current of the inductor should not exceed 260ma and the voltage at the i th pin should not exceed 0.6v. when either one of the conditions is exceeded, the big mosfet will be turned on at the next clock cycle. dropout operation when the input supply voltage decreases toward the output voltage, the rate of change of inductor current during the on cycle decreases. this reduction means that the p-channel mosfets will remain on for more than one oscillator cycle since the i comp is not tripped. further reduction in input supply voltage will eventually cause the p-channel mosfet to be turned on 100%, i.e., dc. the output voltage will then be determined by the input voltage minus the voltage drop across the mosfets. typically under dropout, both the power mosfets are on since the voltage on the i th pin is greater than 0.6v. frequency synchronization a phase-locked loop (pll) is available on the ltc1434 to allow the oscillator to be synchronized to an external source connected to the pllin pin. the output of the phase detector at the pll lpf pin is also the control input of the oscillator, which operates over a 0v to 2.4v range corresponding to C 30% to + 30% in the oscillators center frequency. when locked, the pll aligns the turn-on of the mosfets to the rising edge of the synchronizing signal. when the pllin is left open, pll lpf goes low, forcing the oscillator to minimum frequency. power-on reset the por pin is an open-drain output which pulls low when the regulator is out of regulation. when the output voltage rises to within 5% of regulation, a timer is started which releases por after 2 16 (65536) oscillator cycles. in shut- down the por output is pulled low. short-circuit protection when the output is shorted to ground, the frequency of the oscillator will be reduced to about 1/4.5 of its designed rate. this low frequency allows the inductor current to discharge, thereby preventing runaway. the oscillators frequency will gradually increase to its designed rate when the output voltage increases above 0.65v. applicatio n s i n for m atio n wu u u the basic ltc1434 application circuit is shown in figure 1. external component selection is driven by the load requirement and begins with the selection of c osc and l. next, the schottky diode d1 is selected followed by c in and c out . c osc selection for operating frequency the ltc1433/ltc1434 use a constant frequency archi- tecture with the frequency determined by an external oscillator capacitor c osc . during the on-time, c osc is charged by a fixed current plus an additional current which is proportional to the output voltage of the phase detector (v pll lpf on ltc1434). when the voltage on the c osc capacitor reaches 1.19v, it is reset to ground. the process then repeats. the value of c osc is calculated from the desired operating frequency. assume the phase-locked loop has no external oscillator input, i.e. v pll lpf = 0v. cpf frequency khz osc () = ? ? ? () ? ? 137 10 11 4 . a graph for selecting c osc vs frequency is given in figure 2. for the ltc1433, the expression above is also appli- cable since its oscillator is internally set up to run at a condition equal to v pll lpf = 0v. therefore when using the graph for determining the capacitance value for the oscil- lator frequency, the v pll lpf = 0v curve should be used for ltc1433.
8 ltc1433/ltc1434 ltc1433/ltc1434 are used at 100% duty cycle with low input voltages. inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies permit the use of a smaller inductor for the same amount of inductor ripple current. however, this is at the expense of efficiency due to an increase in mosfet gate charge losses. the inductor value has a direct effect on ripple current. the ripple current d i l decreases with higher inductance or frequency and increases with higher v in or v out : d i fl v v v l out out in = ()( ) ? ? ? ? 1 1 core losses are dependent on the peak-to-peak ripple current and core material. hence, by choosing a larger inductance the peak-to-peak inductor ripple current will decrease, therefore decreasing core loss. to further re- duce losses, low core loss material such as molypermalloy or kool m m ? can be chosen as the inductor core material. an indirect way that the inductor affects efficiency is through the usage of the big p-channel at low load currents. lower inductance values will result in high peak inductor current. because one of the conditions that determines the turning on of the large p-channel is peak current, this will result in the usage of the large p-channel even though the load current is low. hence, efficiency at low load current will be affected. see efficiency consider- ations. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m m cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. applicatio n s i n for m atio n wu u u figure 2. selecting c osc for oscillator frequency kool m m is a registered trademark of magnetics, inc. capacitance on c osc pin (pf) 0 frequency (khz) 400 500 600 150 1433/34 f02 300 200 50 100 200 100 0 700 v plllpf = 1.19v v plllpf = 2.5v v plllpf = 0v another important point to note is that at a low supply voltages, the r ds(on) of the p-channel switch increases (see typical performance characteristics). therefore, the user should calculate the power dissipation when the as the operating frequency is increased the gate charge losses will be higher, reducing efficiency. the maximum recommended switching frequency is 700khz. when us- ing figure 2 for synchronizable applications, the value of c osc is selected corresponding to a frequency 30% below your center frequency (see phase-locked loop and fre- quency synchronization). low supply operation the ltc1433/ltc1434 can function down to 3v and the maximum allowable output current is also reduced at low input voltages. figure 3 shows the amount of change as the supply is reduced down to 2.5v. the minimum guar- anteed input supply is 3v. supply voltage (v) 4.0 maximum output current (%) 70 80 1433/34 f03 60 50 3.5 3.0 2.5 100 90 not recommended figure 3. maximum allowable output current vs supply voltage
9 ltc1433/ltc1434 ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manu- facturer is kool m m . toroids are very space efficient, especially when you can use several layers of wire. be- cause they generally lack a bobbin, mounting is more difficult. however, designs for surface mount are available which do not increase the height significantly. catch diode selection the catch diode carries load current during the off-time. the average diode current is therefore dependent on the p-channel switch duty cycle. at high input voltages the diode conducts most of the time. as v in approaches v out the diode conducts only a small fraction of the time. the most stressful condition for the diode is when the output is short circuited. under this condition the diode must safely handle i peak at close to 100% duty cycle. a fast switching diode must also be used to optimize efficiency. schottky diodes are a good choice for low forward drop and fast switching times. most ltc1433/ltc1434 circuits will be well served by either a 1n5818, an mbrs130lt3 or an mbrm5819 schottky diode. c in and c out selection in continuous mode, the source current of the p-channel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: c required in ii vvv v rms max out in out in ? - () [] 12 / this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. the selection of c out is driven by the required effective series resistance (esr). typically once the esr require- ment is satisfied the capacitance is adequate for filtering. the output ripple ( d v out ) is determined by: dd v i esr fc out l out ?+ ? ? ? ? 1 4 where f = operating frequency, c out = output capacitance and d i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since d i l increases with input voltage. for the ltc1433/ltc1434, the general rule for proper operation is: c out required esr < 0.25 w manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance through-hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr/size ratio of any aluminum electrolytic at a some- what higher price. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. in surface mount applications multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application. aluminum elec- trolytic and dry tantalum capacitors are both available in surface mount configurations. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. other capacitor types include sanyo os-con, nichicon pl series and panasonic sp series. consult the manufacturer for other specific recommendations. applicatio n s i n for m atio n wu u u
10 ltc1433/ltc1434 applicatio n s i n for m atio n wu u u efficiency considerations since there are two separate pins for the drain of the small and large p-channel switch, we could utilize two induc- tors to further enhance the efficiency of the regulator over the low load current range. figure 4 shows the circuit connection.(also refer to the typical applications sec- tion.) figure 4. using two inductors for higher low current efficiency bsw ssw d1 d2 1433/34 f04 l2 l1 ltc1433/ ltc1434 to reduce core losses, the user can use a higher value inductor on the small p-channel switch. since this switch only carries a small part of the overall current, the user can still use a small physical size inductor without sacrificing on copper losses. the schottky diode can also be chosen with a lower current rating. for the graph in figure 5, a coilcraft dt1608c series inductor is used along with a mbrs0520lt3 schottky diode on the ssw pin. as can be seen from figure 5, the average efficiency gain over the region where the small p-channel is on is about 3%. load current (a) 0.001 60 efficiency (%) 70 80 0.01 0.1 1 1433/34 ?f05 50 40 100 90 v in = 5v v in = 9v one 22 m h inductor on ssw and bsw 100 m h on ssw 22 m h on bsw v out = 3.3v c osc = 47pf figure 5. efficiency comparison between single inductor and dual inductor hence, the dual inductor configuration is good for the user who requires as high an efficiency as possible at low load while retaining constant frequency operation. output voltage programming the ltc1433/ltc1434 family all have pin selectable out- put voltage programming. the output voltage is selected by the v prog pin as follows: v prog = 0v v out = 3.3v v prog = v in v out = 5v v prog = open (dc) v out = adjustable the ltc1433/ltc1434 family also has remote output voltage sense capability. the top of the internal resistive divider is internally connected to v osense . for fixed output voltage applications, the v osense pin is connected to the output voltage as shown in figure 6 . when using an external resistive divider, the v prog pin is left open dc and the v osense pin is connected to the feedback resistors as shown in figure 7. to prevent stray pickup, a 100pf capacitor is suggested across r1 located close to the ltc1433/ltc1434. r1 r2 open (dc) 1433/34 f07 100pf v out v prog sgnd ltc1433/ ltc1434 v osense v out = 1.19v 1 + r2 r1 () figure 7. ltc1433/ltc1434 adjustable applications v prog sgnd ltc1433/ ltc1434 1433/34 f06 c out v out gnd: v out = 3.3v v in : v out = 5v + v osense figure 6. ltc1433/ltc1434 fixed output applications
11 ltc1433/ltc1434 applicatio n s i n for m atio n wu u u power-on reset function (por) the power-on reset function monitors the output voltage and turns on an open-drain device when it is out of regulation. an external pull-up resistor is required on the por pin. when power is first applied or when coming out of shutdown, the por output is pulled to ground. when the output voltage rises above a level which is 5% below the regulated output value, an internal counter starts. after counting 2 16 (65536) clock cycles the por pull-down device turns off. the por output will go low whenever the output voltage drops below 7.5% of its regulated value for longer than approximately 30 m s, signaling an out-of-regulation condi- tion. in shutdown the por output is pulled low even if the regulators output is held up by an external source. run/soft start function the run/ss pin is a dual purpose pin which provides the soft start function and a means to shut down the ltc1433/ ltc1434. soft start reduces input surge currents by providing a gradual ramp-up of the internal current limit. power supply sequencing can also be accomplished using this pin. an internal 3 m a current source charges up an external capacitor c ss. when the voltage on run/ss reaches 1.3v the ltc1433/ltc1434 begins operating. as the voltage on run/ss continues to ramp from 1.3v to 2.4v the internal current limit is also ramped at a proportional linear rate. the current limit begins at approximately 350ma (at v run/ ss = 1.3v) and ends at 1.2a (v run/ss = 2.4v). the output voltage thus ramps up slowly, charging the output capacitor while input surge currents are re- duced. if run/ss has been pulled all the way to ground there is a delay of approximately 0.5s/ m f before starting, followed by a like time to reach full current. t delay = 5(10 5 )c ss seconds by pulling the run/ss pin below 1.3v, the ltc1433/ ltc1434 are put in low current shutdown. this pin can be driven directly from logic as shown in figure 8. diode d1 in figure 8 reduces the start delay but allows c ss to ramp up slowly providing the soft start function. this diode can be deleted if soft start is not needed. the run/ss pin has an internal 6v zener clamping the voltage on this pin (see functional diagram). 1433/34 f08 c ss d1 run/ss c ss run/ss figure 8. run/ss pin interfacing phase-locked loop and frequency synchronization the ltc1434 has an internal voltage-controlled oscilla- tor and phase detector comprising a phase-locked loop. this allows the mosfet turn-on to be locked to the rising edge of an external source. the frequency range of the voltage-controlled oscillator is 30% around the center frequency f o . the value of c osc is calculated from the desired operating frequency (f o ) with the following expression (assuming the phase-locked loop is locked, i.e v pll lpf = 1.19v): c frequency osc pf khz () = ? ? ? () ? ? 206 10 11 4 . instead of using the above expression, figure 2 graphi- cally shows the relationship between the oscillator fre- quency and the value of c osc under various voltage conditions at the pll lpf pin. the phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal oscillators. this type of phase detector will not lock up on input frequencies close to the harmonics of the v co center frequency. the pll hold-in range d f h is equal to the capture range, d f h = d f c = 0.3f o. the output of the phase detector is a pair of complemen- tary current sources charging or discharging the external filter network on the pll lpf pin. the relationship between the voltage on the pll lpf pin and operating frequency is shown in figure 9. a simplified block diagram is shown in figure 10.
12 ltc1433/ltc1434 applicatio n s i n for m atio n wu u u figure 10. phase-locked loop block diagram pllin 50k 1433/34 f10 pll lpf c osc phase detector osc r lp c lp c osc external frequency 2.4v digital phase/ frequency detector v plllpf (v) 0 frequency (khz) 1.3f o 0.7f o 1433/34 f09 1.5 2.0 1.0 0.5 2.5 f o figure 9. relationship between oscillator frequency and voltage at pll lpf pin if the external frequency (v pllin ) is greater than the center frequency f 0 , current is sourced continuously, pulling up the pll lpf pin. when the external frequency is less than f 0 , current is sunk continuously, pulling down the pll lpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase differ- ence. thus the voltage on the pll lpf pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point the phase comparator output is open and the filter capacitor c lp holds the voltage. the loop filter components c lp and r lp smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp = 10k and c lp is 0.01 m f to 0.1 m f. be sure to connect the low side of the filter to sgnd. the pll lpf pin can be driven with external logic to obtain a 1:1.9 frequency shift. the circuit shown in figure 11 will provide a frequency shift from f o to 1.9f o as the voltage v pll lpf increases from 0v to 2.4v. do not exceed 2.4v on v pll lpf . figure 11. directly driving pll lpf pin pll lpf 2.4v max 3.3v or 5v 1433/34 f11 18k low-battery comparator the ltc1433/ltc1434 have an on-chip, low-battery com- parator which can be used to sense a low-battery condi- tion when implemented as shown in figure 12. the resis- tor divider r3/r4 sets the comparator trip point as follows: v r r lbtrip =+ ? ? ? ? 119 4 3 1 . + v in r4 r3 1433/34 f12 1.19v reference ltc1433/ltc1434 figure 12. low-battery comparator the divided down voltage at the negative (C) input to the comparator is compared to an internal 1.19v reference. a 40mv hysteresis is built in to assure rapid switching. the output is an open-drain mosfet and requires a pull-up resistor to operate. this comparator is active in shutdown. to save more shutdown quiescent current, this compara- tor can be shut down by taking the lbi pin below 0.74v,
13 ltc1433/ltc1434 applicatio n s i n for m atio n wu u u further reducing the current to 15 m a. the low side of the resistive divider should connect to sgnd. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1433/ltc1434. these items are also illustrated graphi- cally in the layout diagram of figure 13. check the follow- ing in your layout: 1. are the signal and power grounds segregated? the ltc1433/ltc1434 signal ground pin must return to the (C) plate of c out . the power ground returns to the anode of the schottky diode and the (C) plate of c in , which should have as short lead lengths as possible. 2. does the ltc1433/ltc1434 v osense pin connect to the (+) plate of c out ? in adjustable applications, the resis- tive divider r1/r2 must be connected between the (+) plate of c out and signal ground. 3. does the (+) plate of c in connect to the power v in as close as possible? this capacitor provides the ac current to the internal p-channel mosfets and their drivers. 4. is the schottky diode closely connected between the power ground and switch pin? 5. keep the switching nodes, ssw and bsw away from sensitive small-signal nodes v osense , pllin, pll lpf, c osc , i th and lbi. design example as a design example, assume v in = 6v, v out = 5v, i max = 400ma and f osc = 200khz. with these requirements we can start choosing all of the important components. with no frequency synchronization required, the ltc1433 can be used for this circuit. from figure 2, the v pll lpf = 0v curve is used to determine the value of the oscillator capacitor. from the graph a value of 50pf will provide the desired frequency. next the inductor value is selected. from the maximum output current vs input supply graph in the typical performance characteristics section, a value of l = 22 m h would be able to meet the requirement for the output load current. for the catch diode, a mbrs130lt3 is selected. figure 13. ltc1434 layout diagram (see board layout check list) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc ssw nc bsw sgnd nc run/ss nc lbo lbi pwrv in sv in pllin pll lpf c osc por i th v osense v prog ltc1434 pgnd c in c ss 0.1 m f output divider required with adjustable version only. connect v osense to v out for fixed output voltage v out c out d1 l1 1433/34 f13 c osc + + bold lines indicate high current paths
14 ltc1433/ltc1434 applicatio n s i n for m atio n wu u u c in will require an rms current rating of at least 0.2a at temperature and c out will require an esr of less than 0.25 w . in most of the applications, the requirements for these capacitors are fairly similar. figure 14 shows the complete circuit along with its effi- ciency curve. latchup prevention (figure 15) in applications where the input supply can momentarily dip below the output voltage, it is recommended that a schottky diode (d2) be connected from v out to v in . this diode will prevent the output capacitor from forward biasing the parasitic diode of the internal monolithic power mosfet, preventing a large amount of current from flowing into the substrate to create a potential latchup condition. figure 14. design example circuit and its efficiency curve 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssw nc bsw nc sgnd run/ss lbo lbi pwrv in sv in c osc por i th v osense v prog ltc1433 pgnd 100 m f* 10v 0.1 m f 0.1 m f 100 m f* 10v d1: mbrs130lt3 l1: sumida cd54-220 * avx tpsd107m010r0100 v out 5v 400ma d1 l1 22 m h power-on reset v in 6v 680pf 5.1k 10k 6800pf 50pf load current (a) 0.001 60 efficiency (%) 70 80 0.01 0.1 1 1433/34 f14 50 40 100 90 v in = 6v v out = 5v c osc = 50pf l = 22 m h + + ltc1434 + d1 d2 c out sw v out v in l 1433/34 f15 figure 15
15 ltc1433/ltc1434 typical applicatio n s n u highest efficiency 3.3v/5v converter 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssw nc bsw nc sgnd run/ss lbo lbi pwrv in pgnd sv in c osc por i th v osense v prog ltc1433 68 m f** 20v 0.1 m f 0.1 m f 100 m f* 10v d1: motorola mbrs0520lt3 d2: motorola mbrs130lt3 l1: coilcraft dt1608c series l2: sumida cd54 series v out d1 l2 22 m h power-on reset v in 3.5v to 12.5v for v out = 3.3v 6v to 12.5v for v out = 5v v prog = 0v, v out = 3.3v v prog = v in , v out = 5v 100pf 5.1k 100k 6800pf 1433/34 ta02 d2 l1 100 m h 680pf * avx tpsd107m010r0100 ** avx tpse686m020r0150 + + positive-to-negative C 5v converter 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssw nc bsw nc sgnd run/ss lbo lbi pwrv in pgnd sv in c osc por i th v osense v prog ltc1433 100 m f** 16v 0.1 m f 0.01 m f 100 m f* 10v d1: motorola mbrs130lt3 l1: coilcraft do3316 series v out ?v d1 v in 3.5v to 7.5v 100pf 5.1k 6800pf 1433/34 ta03 680pf * avx tpsd107m010r0100 ** avx tpse107m016r0100 l1 68 m h v in (v) 3.0 4.0 5.0 6.0 7.0 7.5 i out(max) (ma) 180 240 290 340 410 420 + +
16 ltc1433/ltc1434 typical applicatio n s n u negative boost converter 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssw nc bsw nc sgnd run/ss lbo lbi pwrv in pgnd sv in c osc por i th v osense v prog ltc1433 0.1 m f 100 m f* 16v 100 m f* 16v d1: motorola mbrs130lt3 l1: coilcraft do3316 series v out ?v v in 3v to 7v d1 100pf 5.1k 50k 1% 310k 1% 6800pf 1433/34 ta05 68 m f** 20v 0.1 m f 680pf 100pf * avx tpse107m016r0100 ** avx tpse686m020r0150 l1 100 m h v in (v) ? ? ? ? ? i out(max) (ma) 180 300 400 540 680 + + + ultralow output ripple 5v to C 1.25v mr head amplifier supply 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssw nc bsw nc sgnd run/ss lbo lbi pwrv in pgnd sv in c osc por i th v osense v prog ltc1433 100 m f* 10v 0.1 m f 0.1 m f 100 m f* 10v d1: motorola mbrm5819 l1: sumida cd54 series l2: j.w. miller pm20-r33m * avx tpsd107m010r0100 v out ?.25v 280ma d1 l1 22 m h power-on reset v in 5v 680pf 100pf 5.1k 23.8k 1% 1.2k 1% 10k 6800pf 100pf 1433/34 ta04 100 m f* 10v l2 0.33 m h + + +
17 ltc1433/ltc1434 typical applicatio n s n u 9v to 12v, C 12v outputs 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssw nc bsw nc sgnd run/ss lbo lbi pwrv in pgnd sv in c osc por i th v osense v prog ltc1433 68 m f* 20v 0.1 m f 0.1 m f 47 m f** 68 m f* 20v 68 m f* 20v v out 12v power-on reset v in 4.5v to 12.5v 50pf 1k 30k 100k 6800pf 1433/34 ta07 d2 100pf v out ?2v 301k 1% 34k 1% 1n914 si6447dq 680pf top view 3 1 2 4 l1b l1b l1a l1a d1, d2: motorola mbrs130lt3 l1a, l1b: * avx tpse686m020r0150 ** wima mks2 manufacturer coiltronics dale part no. ctx100-4 lpt4545-101la 96k 100k low-battery trip at v in = 5v l1a 100 m h d1 l1b 100 m h v in (v) 4.5 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 12.5 each output i out(max) (ma) 50 60 70 100 110 130 145 160 200 205 + + +
18 ltc1433/ltc1434 u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) gn16 (ssop) 0398 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.025 (0.635) bsc 0.009 (0.229) ref
19 ltc1433/ltc1434 u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn package 20-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) 0.337 ?0.344* (8.560 ?8.737) gn20 (ssop) 0398 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8910 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 17 18 19 20 15 14 13 12 11 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.025 (0.635) bsc 0.058 (1.473) ref
20 ltc1433/ltc1434 ? linear technology corporation 1996 14334fa lt/tp 1298 2k rev a ? printed in the usa typical applicatio u 5v to 5v outputs 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssw nc bsw nc sgnd run/ss lbo lbi pwrv in pgnd sv in c osc por i th v osense v prog ltc1433 100 m f* 10v 0.1 m f 0.01 m f 4.7 m f** 100 m f* 10v 100 m f* 10v i out(max) = 130ma i out(min) = 10ma v out = 5v i out(max) = 130ma i out(min) = 5ma v out = 5v d1: motorola mbrs130lt3 l1a, l1b: power-on reset v in 5v 50pf 5.1k 100k 6800pf 1433/34 ta06 d2 l1a 20 m h l1b 20 m h 680pf * avx tpsd107m010r0100 ** wima mks2 top view 3 1 2 4 l1b l1b l1a l1a manufacturer coiltronics dale part no. ctx20-4 lpt4545-200la d1 1 2 34 + + + part number description comments lt ? 1074/lt1076 step-down switching regulators 100khz, 5a (lt1074) or 2a (lt1076) internal switch ltc1174/ltc1174-3.3/ high efficiency step-down and inverting dc/dc converters burst mode tm operation ltc1174-5 ltc1265 1.2a high efficiency step-down dc/dc converter burst mode operation lt1375/lt1376 1.5a, 500khz step-down switching regulators high frequency, small inductor, high efficiency switchers, 1.5a switch ltc1474 high efficiency step-down converter low i q = 10 m a, 8-pin msop ltc1435 high efficiency synchronous step-down controller 16-pin narrow so and ssop ltc1436/ltc1436-pll high efficiency low noise synchronous step-down controllers 24-pin narrow and 28-pin ssop ltc1438/ltc1439 dual high efficiency low noise synchronous step-down controllers up to four outputs capability ltc1538-aux dual high efficiency synchronous step-down controller auxiliary linear regulator 5v standby in shutdown ltc1539 dual high efficiency low noise synchronous step-down controller auxiliary linear regulator 5v standby in shutdown ltc1627 high efficiency monolithic synchronous dc/dc converter low supply voltage: 2.65v to 10v, 0.5a burst mode is a trademark of linear technology corporation. related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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